Preface |
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xvii | |
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1 | (12) |
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Definition of data acquisition and control |
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1 | (1) |
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Fundamentals of data acquisition |
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2 | (4) |
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3 | (1) |
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Field wiring and communications cabling |
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3 | (1) |
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3 | (1) |
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Data acquisition hardware |
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4 | (1) |
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Data acquisition software |
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5 | (1) |
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5 | (1) |
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Data acquisition and control system configuration |
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6 | (7) |
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7 | (1) |
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8 | (1) |
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Stand-alone or distributed loggers/controllers |
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9 | (2) |
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IEEE 488 (GPIB) remote programmable instruments |
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11 | (2) |
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Analog and digital signals |
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13 | (23) |
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Classification of signals |
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13 | (4) |
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Digital signals binary signals |
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14 | (1) |
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15 | (2) |
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17 | (1) |
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Transducer characteristics |
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17 | (2) |
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Resistance temperature detectors (RTDs) |
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19 | (3) |
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19 | (1) |
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19 | (1) |
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Measurement circuits and considerations for RTDs |
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20 | (2) |
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22 | (1) |
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22 | (6) |
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Reference junction compensation |
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23 | (1) |
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Isothermal block and compensation cables |
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24 | (1) |
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Thermocouple linearization |
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24 | (1) |
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Thermocouple types and standards |
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25 | (1) |
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Thermocouple construction |
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26 | (1) |
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26 | (1) |
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27 | (1) |
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28 | (1) |
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29 | (7) |
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29 | (1) |
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Quarter bridge configuration |
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30 | (1) |
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Half bridge configuration |
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31 | (1) |
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Full bridge configuration |
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32 | (1) |
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32 | (2) |
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Temperature considerations |
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34 | (1) |
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34 | (2) |
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36 | (31) |
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36 | (1) |
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Types of signal conditioning |
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37 | (7) |
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37 | (1) |
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37 | (1) |
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38 | (6) |
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44 | (1) |
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Classes of signal conditioning |
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44 | (4) |
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Plug-in board signal conditioning |
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44 | (1) |
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Direct connect modular -- two-wire transmitters |
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45 | (1) |
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Distributed I/O -- digital transmitters |
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46 | (2) |
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Field wiring and signal measurement |
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48 | (8) |
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49 | (1) |
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49 | (1) |
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50 | (1) |
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50 | (1) |
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Common mode voltages and CMRR |
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50 | (2) |
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Measuring grounded signal sources |
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52 | (1) |
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53 | (1) |
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53 | (1) |
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Measuring ungrounded signal sources |
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54 | (1) |
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55 | (1) |
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56 | (5) |
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Definition of noise and interference |
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56 | (1) |
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Sources and types of noise |
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56 | (5) |
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61 | (3) |
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Cable shielding and shield earthing |
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61 | (1) |
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62 | (2) |
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Shielded and twisted-pair cable |
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64 | (3) |
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65 | (1) |
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66 | (1) |
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The PC for real time work |
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67 | (52) |
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67 | (1) |
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67 | (5) |
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68 | (1) |
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Microsoft Windows 3.1, 95, 98, 2000 and NT |
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69 | (2) |
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71 | (1) |
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72 | (5) |
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73 | (1) |
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73 | (1) |
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73 | (1) |
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Programmable interrupt controller(s) |
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73 | (2) |
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Initialization required for interrupts |
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75 | (1) |
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I/O devices requesting interrupt service |
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75 | (1) |
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Interrupt service routines |
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76 | (1) |
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77 | (1) |
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Operation of direct memory access (DMA) |
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77 | (6) |
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78 | (1) |
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Initialization required for DMA control |
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79 | (1) |
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I/O devices requesting DMA |
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79 | (1) |
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80 | (1) |
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81 | (2) |
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Repeat string instructions (REP INSW) |
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83 | (1) |
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84 | (12) |
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Data transfer speed (polled I/O, interrupt I/O, DMA) |
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96 | (1) |
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97 | (2) |
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97 | (1) |
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Expanded memory system (EMS) |
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98 | (1) |
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99 | (1) |
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Expansion memory hardware |
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99 | (1) |
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Expansion bus standards (ISA, EISA, PCI, and PXI bus) |
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99 | (13) |
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99 | (9) |
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108 | (1) |
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108 | (1) |
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The PCI, compactPCI and PXI bus |
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109 | (3) |
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112 | (1) |
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112 | (1) |
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112 | (1) |
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Interfacing techniques to the IBM PC |
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113 | (6) |
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114 | (1) |
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115 | (1) |
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116 | (3) |
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Plug-in data acquisition boards |
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119 | (57) |
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119 | (1) |
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120 | (18) |
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120 | (1) |
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121 | (2) |
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123 | (1) |
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123 | (1) |
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124 | (12) |
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136 | (1) |
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136 | (1) |
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137 | (1) |
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Single ended vs differential signals |
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138 | (3) |
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138 | (1) |
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Pseudo-differential configuration |
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139 | (1) |
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140 | (1) |
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Resolution, dynamic range and accuracy of A/D boards |
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141 | (2) |
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141 | (1) |
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141 | (1) |
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142 | (1) |
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Sampling rate and the Nyquist theorem |
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143 | (8) |
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143 | (1) |
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143 | (3) |
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146 | (2) |
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148 | (3) |
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151 | (5) |
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Continuous channel scanning |
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151 | (2) |
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153 | (1) |
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154 | (2) |
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156 | (1) |
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157 | (7) |
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Digital to analog converters |
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158 | (2) |
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Parameters of D/A converters |
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160 | (2) |
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Functional characteristics of D/A boards |
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162 | (1) |
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162 | (1) |
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163 | (1) |
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163 | (1) |
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163 | (1) |
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164 | (2) |
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Interfacing digital inputs/outputs |
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166 | (4) |
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166 | (1) |
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167 | (1) |
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168 | (1) |
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168 | (2) |
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170 | (6) |
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Serial data communications |
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176 | (28) |
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Definitions and basic principles |
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176 | (6) |
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Transmission modes -- simplex and duplex |
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177 | (1) |
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178 | (3) |
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Format of data communications messages |
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181 | (1) |
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182 | (1) |
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RS-232-C interface standard |
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182 | (9) |
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Electrical signal characteristics |
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183 | (3) |
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Interface mechanical characteristics |
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186 | (1) |
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Functional description of the interchange circuits |
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187 | (1) |
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The sequence of operation of the EIA-232 interface |
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188 | (2) |
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Examples of RS-232 interfaces |
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190 | (1) |
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Main features of the RS-232 Interface Standard |
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190 | (1) |
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RS-485 interface standard |
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191 | (2) |
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192 | (1) |
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Comparison of the RS-232 and RS-485 standards |
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193 | (1) |
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194 | (1) |
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Serial interface converters |
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194 | (1) |
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195 | (3) |
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196 | (1) |
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196 | (2) |
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198 | (2) |
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Character redundancy checks |
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199 | (1) |
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199 | (1) |
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199 | (1) |
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Troubleshooting & testing serial data communication circuits |
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200 | (4) |
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201 | (1) |
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201 | (1) |
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202 | (1) |
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202 | (1) |
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The PC as a protocol analyzer |
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202 | (2) |
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Distributed and stand-alone loggers/controllers |
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204 | (30) |
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204 | (1) |
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204 | (5) |
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Programming and logging data using PCMCIA cards |
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205 | (1) |
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206 | (1) |
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Direct connection to the host PC |
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206 | (2) |
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Remote connection to the host PC |
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208 | (1) |
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Stand-alone logger/controller hardware |
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209 | (8) |
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210 | (1) |
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210 | (1) |
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211 | (1) |
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Universal asynchronous receiver/transmitter (UART) |
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212 | (1) |
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213 | (1) |
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Power management circuitry |
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214 | (1) |
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Analog inputs and digital I/O |
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215 | (2) |
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217 | (1) |
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Communications hardware interface |
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217 | (3) |
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217 | (2) |
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219 | (1) |
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Communication bottlenecks and system performance |
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219 | (1) |
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Using Ethernet to connect data loggers |
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220 | (1) |
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Stand-alone logger/controller firmware |
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220 | (1) |
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Stand-alone logger/controller software design |
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221 | (9) |
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ASCII based command formats |
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222 | (1) |
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223 | (1) |
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223 | (1) |
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224 | (1) |
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224 | (2) |
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226 | (3) |
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229 | (1) |
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Data logging and retrieval |
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229 | (1) |
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230 | (1) |
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Considerations in using standalone logger/controllers |
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231 | (1) |
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Stand-alone logger/controllers vs internal systems |
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232 | (2) |
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232 | (1) |
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232 | (2) |
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234 | (18) |
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234 | (1) |
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Electrical and mechanical characteristics |
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235 | (1) |
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Physical connection configurations |
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236 | (1) |
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237 | (1) |
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238 | (2) |
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239 | (1) |
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Interface management lines |
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239 | (1) |
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240 | (1) |
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240 | (1) |
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241 | (2) |
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242 | (1) |
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242 | (1) |
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Terminating data messages |
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242 | (1) |
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Sending and receiving data |
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243 | (1) |
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243 | (5) |
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Requirements of IEEE 488.2 controllers |
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243 | (1) |
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IEEE 488.2 control sequences |
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244 | (1) |
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244 | (2) |
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Device interface capabilities |
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246 | (1) |
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246 | (1) |
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247 | (1) |
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Standard commands for programmable instruments (SCPI) |
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248 | (4) |
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IEEE 488.2 common commands required by the SCPI |
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248 | (1) |
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249 | (1) |
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The SCPI programming command model |
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249 | (2) |
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SCPI hierarchical command structure |
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251 | (1) |
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252 | (19) |
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Ethernet and fieldbuses for data acquisition |
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252 | (1) |
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253 | (7) |
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253 | (3) |
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256 | (1) |
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257 | (1) |
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258 | (1) |
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100 Base-T (100 Base-TX, T4, FX, T2) |
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258 | (2) |
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260 | (3) |
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263 | (1) |
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Difference between 802.3 and Ethernet |
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264 | (1) |
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265 | (1) |
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265 | (3) |
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Length of the cable segment |
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265 | (1) |
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Maximum transceiver cable length |
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266 | (1) |
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266 | (1) |
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Maximum transmission path |
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266 | (1) |
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267 | (1) |
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267 | (1) |
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268 | (1) |
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268 | (3) |
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The universal serial bus (USB) |
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271 | (14) |
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271 | (1) |
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271 | (6) |
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272 | (1) |
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273 | (1) |
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The connectors (Type A and B) |
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274 | (1) |
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Low-speed cables and high-speed cables |
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274 | (1) |
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274 | (1) |
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275 | (1) |
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Host hub controller hardware and driver |
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275 | (1) |
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276 | (1) |
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276 | (1) |
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276 | (1) |
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277 | (4) |
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278 | (1) |
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278 | (1) |
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279 | (1) |
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280 | (1) |
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280 | (1) |
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281 | (2) |
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282 | (1) |
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282 | (1) |
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Application layer (user layer) |
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283 | (1) |
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283 | (2) |
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284 | (1) |
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285 | (7) |
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Open and closed loop control |
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285 | (5) |
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285 | (1) |
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Fluid level closed loop control system |
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286 | (1) |
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286 | (2) |
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Transient performance -- step response |
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288 | (1) |
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289 | (1) |
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289 | (1) |
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Manual control -- bumpless transfer |
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289 | (1) |
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Capturing high speed transient data |
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290 | (2) |
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A/D board operation and memory requirements |
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290 | (1) |
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Trigger modes (pre- and post-triggering) |
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290 | (1) |
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290 | (2) |
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292 | (13) |
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292 | (1) |
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293 | (1) |
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293 | (2) |
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293 | (1) |
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294 | (1) |
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Direct memory access (DMA) |
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294 | (1) |
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Multi-functional and transparent |
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294 | (1) |
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294 | (1) |
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294 | (1) |
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295 | (1) |
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295 | (1) |
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295 | (2) |
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295 | (1) |
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295 | (1) |
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296 | (1) |
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296 | (1) |
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296 | (1) |
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296 | (1) |
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296 | (1) |
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296 | (1) |
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297 | (1) |
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297 | (1) |
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297 | (1) |
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297 | (1) |
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297 | (1) |
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298 | (1) |
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298 | (1) |
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298 | (4) |
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299 | (1) |
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299 | (1) |
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299 | (1) |
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300 | (1) |
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I/O with direct memory access |
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300 | (1) |
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ATA interface (AT attachment) |
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301 | (1) |
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AIMS interface (auto-indexing mass storage) |
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302 | (1) |
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302 | (1) |
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303 | (1) |
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PC Card enablers and support software |
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303 | (1) |
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304 | (1) |
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Magazine list and PCMCIA address |
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304 | (1) |
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Personal Computer Memory Card International Association |
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304 | (1) |
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305 | (27) |
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Appendix B IBM PC bus specifications |
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332 | (17) |
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332 | (1) |
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333 | (1) |
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333 | (1) |
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334 | (1) |
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B.4 8259 interrupt controller |
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334 | (2) |
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B.5 8253 / 8254 counter/timer |
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336 | (8) |
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B.6 Bus signal information |
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344 | (2) |
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346 | (1) |
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B.8 Centronics interface standard |
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347 | (2) |
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Appendix C Review of the Intel 8255 PPI chip |
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349 | (15) |
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C.1 DIO0CTRL -- control register of the 8255 |
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351 | (1) |
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C.2 DIOA -- port A of the 8255 (offset 0, read/write) |
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352 | (1) |
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C.3 DIOB -- port B of the 8255 (offset 1, read/write) |
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353 | (1) |
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C.4 DIOC -- port C of the 8255 (offset 2, read/write) |
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353 | (2) |
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355 | (1) |
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355 | (1) |
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355 | (1) |
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356 | (2) |
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C.9 Mode 2: strobed bi-directional bus I/O |
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358 | (1) |
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359 | (2) |
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C.11 Single-bit set/reset |
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361 | (1) |
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C.12 Mixed mode programming |
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361 | (1) |
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C.13 8255-2 mode 1 and 2 timing diagrams |
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362 | (2) |
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Appendix D Review of the Intel 8254 timer-counter chip |
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364 | (13) |
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364 | (2) |
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366 | (1) |
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366 | (1) |
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366 | (1) |
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366 | (3) |
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TCCTRL timer/counter control register (offset 3, write only) |
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366 | (1) |
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367 | (1) |
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368 | (1) |
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368 | (1) |
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TCO - timer/counter 0 (offset 0, read/write) |
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369 | (1) |
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TC1 - timer/counter 1 (offset 1, read/write) |
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369 | (1) |
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TC2 - timer/counter 2 (offset 2, read/write) |
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369 | (1) |
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D.3 Programming a counter |
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369 | (1) |
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370 | (1) |
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370 | (1) |
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370 | (1) |
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370 | (3) |
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371 | (1) |
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371 | (1) |
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371 | (1) |
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372 | (1) |
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Counter status information |
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372 | (1) |
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Latching both status and current count |
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373 | (1) |
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D.5 Counter mode definitions |
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373 | (3) |
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Mode 0: interrupt on terminal count |
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373 | (1) |
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Mode 1: hardware re-triggerable one-shot |
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374 | (1) |
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374 | (1) |
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Mode 3: square wave generator |
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374 | (1) |
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Mode 4: software-triggered strobe |
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375 | (1) |
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Mode 5: hardware-triggered strobe |
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375 | (1) |
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376 | (1) |
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Appendix E Thermocouple tables |
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377 | (12) |
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377 | (1) |
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378 | (1) |
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378 | (1) |
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379 | (1) |
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380 | (1) |
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380 | (1) |
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381 | (1) |
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381 | (1) |
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382 | (1) |
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383 | (1) |
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384 | (1) |
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385 | (1) |
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386 | (1) |
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387 | (1) |
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388 | (1) |
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Appendix F Number systems |
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|
389 | (9) |
|
|
389 | (1) |
|
F.2 A generalized number system |
|
|
389 | (1) |
|
|
390 | (2) |
|
F.3.1 Conversion between decimal and binary numbers |
|
|
391 | (1) |
|
|
392 | (1) |
|
F.4.1 Conversion between binary and hexadecimal |
|
|
393 | (1) |
|
|
393 | (1) |
|
|
394 | (1) |
|
F.7 FBinary coded octal systems |
|
|
394 | (1) |
|
F.8 Internal representation of information |
|
|
395 | (1) |
|
|
395 | (1) |
|
F.8.2 Alphanumeric data representation |
|
|
396 | (1) |
|
|
396 | (2) |
|
Appendix G GPIB (IEEE-488) mnemonics & their definitions |
|
|
398 | (5) |
Index |
|
403 | |