Fundamentals of Computer Organization and Architecture & Advanced Computer Architecture and Parallel Processing, 2 Volume Set,9780471703808

Fundamentals of Computer Organization and Architecture & Advanced Computer Architecture and Parallel Processing, 2 Volume Set

by ;
Edition: 1st
ISBN13: 9780471703808
ISBN10: 047170380X
Format: Hardcover
Pub. Date: 2005-03-14
Publisher(s): Wiley-Interscience
  • Free Shipping Icon

    Free Shipping On All Orders!*

    Free economy shipping applies to all orders shipped to residential addresses. Orders shipped to campus receive free standard shipping. Free shipping offers do not apply to Marketplace items.

List Price: $312.47

Buy New

Usually Ships in 3-4 Business Days
$312.16
Add to Cart

Rent Textbook

Select for Price
Add to Cart
There was a problem. Please try again later.

Used Textbook

We're Sorry
Sold Out

eTextbook

We're Sorry
Not Available

Summary

This two-volume set provides comprehensive coverage of the field of computer organization and architecture.

Author Biography

MOSTAFA ABD-EL-BARR, PhD, is currently a professor and chairman of the Department of Information Science at Kuwait University. He has co-authored two other books, published more than 120 papers, and served as chair for a number of international conferences and symposia.

HESHAM EL-REWINI, PhD, PE, is a full professor and chairman of the Department of Computer Sciences and Engineering at Southern Methodist University (SMU). He has co-authored several books, published numerous research papers in journals and conference proceedings, and chaired many international conferences.

Table of Contents

Preface xi
Introduction to Computer Systems
1(14)
Historical Background
2(2)
Architectural Development and Styles
4(1)
Technological Development
5(1)
Performance Measures
6(5)
Summary
11(4)
Exercises
12(2)
References and Further Reading
14(1)
Instruction Set Architecture and Design
15(22)
Memory Locations and Operations
15(3)
Addressing Modes
18(8)
Instruction Types
26(5)
Programming Examples
31(2)
Summary
33(4)
Exercises
34(1)
References and Further Reading
35(2)
Assembly Language Programming
37(22)
A Simple Machine
38(2)
Instructions Mnemonics and Syntax
40(3)
Assembler Directives and Commands
43(1)
Assembly and Execution of Programs
44(3)
Example: The X86 Family
47(8)
Summary
55(4)
Exercises
56(1)
References and Further Reading
57(2)
Computer Arithmetic
59(24)
Number Systems
59(4)
Integer Arithmetic
63(11)
Floating-Point Arithmetic
74(5)
Summary
79(4)
Exercises
79(2)
References and Further Reading
81(2)
Processing Unit Design
83(24)
CPU Basics
83(2)
Register Set
85(4)
Datapath
89(2)
CPU Instruction Cycle
91(4)
Control Unit
95(9)
Summary
104(3)
Exercises
104(2)
References
106(1)
Memory System Design I
107(28)
Basic Concepts
107(2)
Cache Memory
109(21)
Summary
130(5)
Exercises
131(2)
References and Further Reading
133(2)
Memory System Design II
135(26)
Main Memory
135(7)
Virtual Memory
142(14)
Read-Only Memory
156(2)
Summary
158(3)
Exercises
158(2)
References and Further Reading
160(1)
Input--Output Design and Organization
161(24)
Basic Concepts
162(2)
Programmed I/O
164(3)
Interrupt-Driven I/O
167(8)
Direct Memory Access (DMA)
175(2)
Buses
177(4)
Input--Output Interfaces
181(1)
Summary
182(3)
Exercises
183(1)
References and Further Reading
183(2)
Pipelining Design Techniques
185(30)
General Concepts
185(2)
Instruction Pipeline
187(14)
Example Pipeline Processors
201(6)
Instruction-Level Parallelism
207(2)
Arithmetic Pipeline
209(4)
Summary
213(2)
Exercises
213(2)
References and Further Reading
215(1)
Reduced Instruction Set Computers (RISCs)
215(20)
RISC/CISC Evolution Cycle
217(1)
RISCs Design Principles
218(2)
Overlapped Register Windows
220(1)
RISCs Versus CISCs
221(2)
Pioneer (University) RISC Machines
223(4)
Example of Advanced RISC Machines
227(5)
Summary
232(3)
Exercises
233(1)
References and Further Reading
233(2)
Introduction to Multiprocessors
235(24)
Introduction
235(1)
Classification of Computer Architectures
236(8)
SIMD Schemes
244(2)
MIMD Schemes
246(6)
Interconnection Networks
252(2)
Analysis and Performance Metrics
254(1)
Summary
254(5)
Exercises
255(1)
References and Further Reading
256(3)
Index 259(8)
Introduction to Advanced Computer Architecture and Parallel Processing
1(18)
Four Decades of Computing
2(2)
Flynn's Taxonomy of Computer Architecture
4(1)
SIMD Architecture
5(1)
MIMD Architecture
6(5)
Interconnection Networks
11(4)
Chapter Summary
15(4)
Problems
16(1)
References
17(2)
Multiprocessors Interconnection Networks
19(32)
Interconnection Networks Taxonomy
19(1)
Bus-Based Dynamic Interconnection Networks
20(4)
Switch-Based Interconnection Networks
24(9)
Static Interconnection Networks
33(8)
Analysis and Performance Metrics
41(4)
Chapter Summary
45(6)
Problems
46(2)
References
48(3)
Performance Analysis of Multiprocessor Architecture
51(26)
Computational Models
51(4)
An Argument for Parallel Architectures
55(3)
Interconnection Networks Performance Issues
58(5)
Scalability of Parallel Architectures
63(4)
Benchmark Performance
67(5)
Chapter Summary
72(5)
Problems
73(1)
References
74(3)
Shared Memory Architecture
77(26)
Classification of Shared Memory Systems
78(2)
Bus-Based Symmetric Multiprocessors
80(1)
Basic Cache Coherency Methods
81(2)
Snooping Protocols
83(6)
Directory Based Protocols
89(7)
Shared Memory Programming
96(3)
Chapter Summary
99(4)
Problems
100(1)
References
101(2)
Message Passing Architecture
103(24)
Introduction to Message Passing
103(2)
Routing in Message Passing Networks
105(4)
Switching Mechanisms in Message Passing
109(5)
Message Passing Programming Models
114(3)
Processor Support for Message Passing
117(1)
Example Message Passing Architectures
118(4)
Message Passing Versus Shared Memory Architectures
122(1)
Chapter Summary
123(4)
Problems
123(1)
References
124(3)
Abstract Models
127(30)
The PRAM Model and Its Variations
127(2)
Simulating Multiple Accesses on an EREW PRAM
129(2)
Analysis of Parallel Algorithms
131(2)
Computing Sum and All Sums
133(3)
Matrix Multiplication
136(3)
Sorting
139(1)
Message Passing Model
140(6)
Leader Election Problem
146(1)
Leader Election in Synchronous Rings
147(7)
Chapter Summary
154(3)
Problems
154(1)
References
155(2)
Network Computing
157(24)
Computer Networks Basics
158(3)
Client/Server Systems
161(5)
Clusters
166(4)
Interconnection Networks
170(5)
Cluster Examples
175(2)
Grid Computing
177(1)
Chapter Summary
178(3)
Problems
178(2)
References
180(1)
Parallel Programming in the Parallel Virtual Machine
181(24)
PVM Environment and Application Structure
181(4)
Task Creation
185(3)
Task Groups
188(2)
Communication Among Tasks
190(6)
Task Synchronization
196(2)
Reduction Operations
198(2)
Work Assignment
200(1)
Chapter Summary
201(4)
Problems
202(1)
References
203(2)
Message Passing Interface (MPI)
205(30)
Communicators
205(4)
Virtual Topologies
209(4)
Task Communication
213(4)
Synchronization
217(3)
Collective Operations
220(5)
Task Creation
225(3)
One-Sided Communication
228(3)
Chapter Summary
231(4)
Problems
231(2)
References
233(2)
Scheduling and Task Allocation
235(32)
The Scheduling Problem
235(3)
Scheduling DAGs without Considering Communication
238(4)
Communication Models
242(2)
Scheduling DAGs with Communication
244(4)
The NP-Completeness of the Scheduling Problem
248(2)
Heuristic Algorithms
250(6)
Task Allocation
256(6)
Scheduling in Heterogeneous Environments
262(5)
Problems
263(1)
References
264(3)
Index 267

An electronic version of this book is available through VitalSource.

This book is viewable on PC, Mac, iPhone, iPad, iPod Touch, and most smartphones.

By purchasing, you will be able to view this book online, as well as download it, for the chosen number of days.

Digital License

You are licensing a digital product for a set duration. Durations are set forth in the product description, with "Lifetime" typically meaning five (5) years of online access and permanent download to a supported device. All licenses are non-transferable.

More details can be found here.

A downloadable version of this book is available through the eCampus Reader or compatible Adobe readers.

Applications are available on iOS, Android, PC, Mac, and Windows Mobile platforms.

Please view the compatibility matrix prior to purchase.